Publications

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On the Effectiveness of Piecewise Activation Approximations for Long-Term Short-Memory Networks, ISVLSI ,2025 (to be submitted)

Simplifying Activations with Linear Approximations in Neural Networks, Memories - Materials, Devices, Circuits and Systems, 2024 (2nd Revision),

AN OPEN SOURCE FRAMEWORK FOR OFFLOADING BIG DATA AND AI TASKS (OFFLOAD) TO HETEROGENEOUS COMPUTE UNITS, MS Thesis, 2024,

Accelerating PageRank Algorithmic Tasks with mIPU, Proceedings of the IEEE Rebooting Computing Conference, December 2024 (Accepted),

Messaging-based Intelligent Processing Unit (m-IPU) for next generation AI computing, IEEE Transactions on Computer Aided Systems (Under Review),

An Opensource Framework for Offloading Big Data and AI Tasks (OFFLOAD) to Heterogenous Compute Units, IEEE Transactions on Computer Aided Systems (Under Review),

A Review of Crosstalk Polymorphic Circuits and their Scalability, Memories - Materials, Devices, Circuits and Systems,(2023)

A Secure and Privacy Preserving Biometric Template Protection Technique, 22nd International Conference of the Biometrics Special Interest Group (BIOSIG 2023) (Under Review),

A Diffuse Optical Tomography based Wearable System for Lower Wrist, 22nd International Conference of the Biometrics Special Interest Group (BIOSIG 2023) (Best Poster Award),

Analysis of fNIRS as a Biometric Modality, The IEEE International Joint Conference on Biometrics (IJCB), 2023,

Unsupervised Adversarial Intrusion Detection for Securing Internet of Things Networks, ,Springer Journal of Hardware and Systems Security (under review), 2023

A Messaging based Intelligent Computing Approach for Machine Learning Applications, ,Online Archive

On circuit developments to enable large scale circuit design while computing with noise, ,Elsevier Integration, V 84, Pages 62-71

DOI: j.vlsi.2022.01.002

A Neoteric Approach for Logic with Embedded Memory Leveraging Crosstalk Computing, ACM Transactions on Computer Systems , 2022,

More than a Device: Function Implementation in a Multi-Gate Junctionless FET Structure, Journal of Electronics and Electrical Engineering, 2022 (Invited Journal),

Turning the Table: Using Reverse Engineering Techniques to Detect FPGA Trojans, ,Springer Journal of Hardware and Systems Security, 2022

Fine-Grained Polymorphic Circuit Framework in Crosstalk Computing, IEEE Transactions on VLSI,2022

Crosstalk Noise based Configurable Computing: A New Paradigm for Digital Electronics, IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE,2021

Crosstalk Logic Circuits with Built-In Memory, IEEE Computer Society Annual Symposium on VLSI ,2021

A New Approach towards Embedded Logic in a Single Device, ,IEEE Nanotechnology Conference, 2020

Crosstalk Noise based Configurable Computing: A New Paradigm for Digital Electronics, ,

Design and Comparison of Crosstalk Circuits at 7nm, IEEE Rebooting Computing Conference,2019

From 180nm to 7nm: Crosstalk Computing Scalability Study, IEEE Electron Device Society S3S Conference,2019 (accepted)

A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs, IEEE/ACM Symposium on Nanoscale Architectures,2019 (accepted)

Fine-Grained Polymorphic Circuit Framework in Crosstalk Computing, IEEE Transactions on Nanotechnology,2019 (Under Review)

Thermal Management Challenges and Mitigation Techniques for Transistor-level 3-D Integration, Elsevier Microelectronics Journal,2019

A New Paradigm for Computing for Digital Electronics under Extreme Environments, IEEE Aerospace Conference,2019

A Novel Analog to Digital Conversion Concept with Crosstalk Computing, 2018 IEEE/ACM International Symposium on Nanoscale Architectures,2018

Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits, 2018 IEEE/ACM International Symposium on Nanoscale Architectures,2018

Interconnect Crosstalk based Computing for Nonlinear Analog Electronics, IEEE Conference on Rebooting Computing,2018

A New Paradigm for Fault-Tolerant Computing with Interconnect Crosstalks, IEEE Conference on Rebooting Computing,2018

New 3-D CMOS Fabric with Stacked Horizontal Nanowires, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,Pp: 1-1, 2018

DOI: 10.1109/TCAD.2018.2848588

Skybridge-3D-CMOS: A Fine-Grained 3D CMOS Integrated Circuit Technology,, IEEE Transactions on Nanotechnology,vol. 16, no. 4, pp. 639-652

DOI: 10.1109/TNANO.2017.2700626

NP-Dynamic Skybridge: A Fine-Grained 3D IC Technology with NP-Dynamic Logic, IEEE Transactions on Emerging Topics in Computing,vol. 5, no. 2, pp. 286-299, April-June 1 2017.

DOI: 10.1109/TETC.2017.2684781

Ultra high density 3D SRAM cell design in Stacked Horizontal Nanowire (SN3D) fabric, 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH),Newport, RI, 2017, pp. 155-161

DOI: 10.1109/NANOARCH.2017.8053734

Linear regression based multi-state logic decomposition approach for efficient hardware implementation, 2017 IEEE/ACM International Symposium on Nanoscale Architectures ,Newport, RI, 2017, pp. 153-154

DOI: 10.1109/NANOARCH.2017.8053715

A New Approach for Multi-Valued Computing Using Machine Learning, 2017 IEEE International Conference on Rebooting Computing (ICRC),Washington, DC, 2017, pp. 1-7

DOI: 10.1109/ICRC.2017.8123646

A New Concept for Computing using Interconnect Crosstalks, 2017 IEEE International Conference on Rebooting Computing (ICRC),Washington, DC, 2017, pp. 1-2.

DOI: 10.1109/ICRC.2017.8123636

Cost Projections and Benefits for Transistor-Level 3-D Integration with Stacked Nanowires, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference,[v1] Wed, 6 Sep 2017,[v2] Thu, 9 Nov 2017

New Thermal Management Approach for Transistor-level 3-D Integration, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference,

Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology, ,

Towards automatic thermal network extraction in 3D ICs, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Beijing,pp. 25-30

DOI: 10.1145/2950067.2950095

Routability in 3D IC Design: Monolithic 3D vs. Skybridge 3D CMOS, Emerging Technologies ,

Fine-grained 3-D CMOS concept using stacked horizontal nanowire,, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH),pp. 151-152

DOI: 10.1145/2950067.2950079

New 3-D CMOS Fabric with Stacked Horizontal Nanowires, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH),Beijing, 2016, pp. 151-152.

DOI: 10.1145/2950067.2950079

Architecting NP-Dynamic Skybridge,, Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, pp. 169-174

DOI: 0.1109/NANOARCH.2015.7180607

Architecting connectivity for fine-grained 3-D vertically integrated circuits, Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures,pp. 175-180

DOI: 10.1109/NANOARCH.2015.7180608

Manufacturing pathway and experimental demonstration for nanoscale fine-grained 3-D integrated circuit fabric, 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO),pp. 1214-1217.

DOI: 10.1109/NANO.2015.7388847

Architecting 3-D integrated circuit fabric with intrinsic thermal management features, Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures,pp. 157-162.

DOI: 10.1109/NANOARCH.2015.7180605

Physically equivalent magneto-electric nanoarchitecture for probabilistic reasoning, IEEE Transactions on Nanotechnology,vol. 14, no. 6, pp : 980-991

DOI: 10.1109/TNANO.2015.2439618

Self-Similar Magneto-Electric Nanocircuit Technology for Probabilistic Inference Engines, IEEE Transactions on Nanotechnology,vol. 14, no. 6, pp. 980-991

DOI: 10.1109/TNANO.2015.2439618

Low-Power Heterogeneous Graphene Nanoribbon-CMOS Multistate Volatile Memory Circuit, ACM Journal on Emerging Technologies in Computing Systems,Vol. No. 12 Issue No. 2 Article No.15 , pp. 15:1-15:18

DOI: 10.1145/2700233

Architecting for Causal Intelligence at Nanoscale, In Computer,vol. 48, no. 12, pp. 54-64

DOI: 10.1109/MC.2015.367

Wave Interference Functions for Neuromorphic Computing, IEEE Transactions on Nanotechnology,vol. 14, no. 4, pp. 742-750

DOI: 10.1109/TNANO.2015.2438231

A new tunnel-FET based RAM concept for ultra-low power applications, NANOARCH '14 Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures,Pages 57-58

Wave-based multi-valued computation framework,, 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH),pp. 171-176.

DOI: 10.1109/NANOARCH.2014.6880494

Heterogeneous graphene–CMOS ternary content addressable memory, Journal of Parallel and Distributed Computing,Volume 74, Issue 6,Pages 2497-2503

Parameter variation sensing and estimation in nanoscale fabrics, ,

Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS, Emerging Technologies;Hardware Architecture,

Experimental Prototyping of Beyond-CMOS Nanowire Computing Fabrics, 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH),pp. 134-139

DOI: 10.1109/NanoArch.2013.6623058

Design of 8T-nanowire RAM array, 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH),pp. 152-157

DOI: 10.1109/NanoArch.2013.6623061

Nanowire field-programmable computing platform,, 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH),pp. 23-25.

DOI: 10.1109/NanoArch.2013.6623032

Integrated Nanowire Systems for Post-CMOS Computing, ,

Ternary Volatile Random Access Memory based on Heterogeneous Graphene-CMOS Fabric, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH),pp. 134-139.

DOI: 10.1109/NanoArch.2013.6623058

Hybrid Graphene Nanoribbon-CMOS tunneling volatile memory fabric, 2011 IEEE/ACM International Symposium on Nanoscale Architectures,pp. 189-195

DOI: 10.1109/NANOARCH.2011.5941503

Nanoscale Application Specific Integrated Circuits, 2011 IEEE/ACM International Symposium on Nanoscale Architectures,pp. 99-106

DOI: 0.1109/NANOARCH.2011.5941490

N3asic-based nanowire volatile RAM, 2011 11th IEEE International Conference on Nanotechnology,pp. 1097-1101

DOI: 0.1109/NANO.2011.6144449

Comparison of fast modular multiplication architectures in FPGA, 2010 International Conference on Anti-Counterfeiting, Security and Identification,pp. 45-48

DOI: 10.1109/ICASID.2010.5551841

Efficient hardware implementation of RSA cryptography, 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication,pp: 316-319

DOI: 10.1109/ICASID.2009.5276895